Course: COMP347 Computer Networks (Revision 10) | Textbook: Kurose & Ross, Computer Networking: A Top-Down Approach (9th ed.)
Upon completion of this tutorial, students should be able to:
Routers are the fundamental building blocks of the Internet's infrastructure. They interconnect networks and forward packets from source to destination. Understanding router architecture is essential for understanding how the data plane operates at the hardware level.
This tutorial provides a comprehensive examination of router internals, including input ports, output ports, switching fabrics, and the routing processor. We will explore how each component contributes to the forwarding pipeline and discuss the design trade‑offs that balance performance, cost, and functionality. We also cover advanced topics such as virtual routing and forwarding (VRF), pipeline parallelism, and the emergence of programmable data planes using P4.
A router consists of four major components:
| Component | Function | Plane |
|---|---|---|
| Input Ports | Receive packets, perform link‑layer processing, look up forwarding table, queue | Data |
| Switching Fabric | Move packets from input ports to output ports | Data |
| Output Ports | Buffer packets, schedule transmission, perform link‑layer encapsulation | Data |
| Routing Processor | Execute routing protocols, maintain forwarding tables, manage router | Control |
In modern routers, the data plane is increasingly implemented in hardware (ASICs, TCAM, network processors) to achieve wire‑speed forwarding, while the control plane runs on general‑purpose CPUs.
Input ports are the entry points for packets arriving at a router. They perform a sequence of operations on each arriving packet:
The forwarding table lookup is the bottleneck in high‑speed routers. Techniques include:
The switching fabric is the internal network that connects input ports to output ports. It is responsible for transferring packets from input to output ports.
| Type | Description | Advantages | Disadvantages |
|---|---|---|---|
| Shared Memory | Packets are copied to a shared memory; the switch determines output port. | Simple, low cost | Memory bandwidth limits throughput; one packet at a time |
| Shared Bus | All ports share a bus; packets are sent over the bus to output ports. | Simple, moderate cost | Bus bandwidth limits throughput; one packet at a time |
| Crossbar | N×N array of crosspoints; multiple simultaneous connections. | High throughput, non‑blocking | Complex scheduling, high cost |
In a crossbar, scheduling is required to resolve conflicts when multiple input ports want to send to the same output port (output contention) or when an input port has multiple packets destined for different outputs (input contention).
Common scheduling algorithms:
In input‑queued switches, HOL blocking occurs when a packet at the front of an input queue is blocked (due to output contention) and prevents packets behind it from being forwarded, even if they are destined for idle outputs. HOL blocking can reduce throughput to about 58% for uniform traffic. Techniques to mitigate HOL blocking:
Output ports prepare packets for transmission onto the outgoing link. Their functions include:
Buffering is necessary because packets may arrive faster than they can be forwarded or transmitted.
The amount of buffering required depends on the traffic characteristics and the speed of the link. A classic rule of thumb: buffer size should be at least the bandwidth‑delay product (BDP) to absorb bursts. For TCP traffic, the buffer size is often set to the product of the link bandwidth and the average RTT. However, large buffers can increase latency (bufferbloat).
The routing processor (route processor) is responsible for control plane functions:
| Metric | Description |
|---|---|
| Throughput | Maximum rate at which packets can be forwarded (bits per second). |
| Latency | Time from packet arrival to departure (store‑and‑forward vs. cut‑through). |
| Line Rate | Speed of each input/output link (e.g., 10 Gbps, 100 Gbps). |
| Port Density | Number of ports supported. |
| Scalability | Ability to add ports and increase capacity. |
| Power Consumption | Watt per Gbps; important for large data centers. |
VRF allows a single router to host multiple independent routing tables, each with its own FIB. This is used in provider networks to separate customer traffic. Each VRF instance has its own forwarding table and routing protocols.
Modern routers use a pipelined architecture where packet processing is divided into multiple stages (e.g., header validation, lookup, switching, output). Each stage is performed by dedicated hardware, allowing high throughput. For example, a 5‑stage pipeline can process one packet per clock cycle per stage, achieving high performance.
P4 (Programming Protocol‑independent Packet Processors) is a language that allows network operators to define the packet processing pipeline for switches and routers. With P4, the data plane can be reprogrammed to support new protocols or features without changing hardware. This enables flexible forwarding, in‑network computing, and rapid innovation.
Q1. Which of the following is NOT a major component of a router?
C) Transport layer processor is not a router component; the router operates at the network layer.
Q2. What is the primary function of the input port's forwarding table lookup?
B) The forwarding lookup maps the destination address to an output port.
Q3. Which switching fabric type allows multiple packets to be forwarded simultaneously?
C) Crossbar provides non‑blocking simultaneous connections.
Q4. What is Head‑of‑Line (HOL) blocking?
B) HOL blocking occurs when a blocked packet at the head of an input queue prevents other packets from being forwarded.
Q5. Which technology is commonly used for high‑speed forwarding table lookup in routers?
B) TCAM (Ternary Content Addressable Memory) enables parallel, single‑cycle lookups.
Q6. Which scheduling algorithm provides fair bandwidth allocation by emulating bit‑wise round‑robin?
D) WFQ provides fair allocation by approximating a fluid model.
Q7. Which drop policy is designed to avoid global synchronization of TCP flows?
B) RED drops packets early to signal congestion, preventing multiple TCP flows from synchronizing their backoff.
Q8. In a crossbar switch, what is the purpose of scheduling?
B) Scheduling resolves output contention and input contention to determine which packets get switched.
Q9. Which component is responsible for executing routing protocols and computing the FIB?
D) The routing processor handles control plane functions.
Q10. What is the advantage of Virtual Output Queuing (VOQ) over simple input queuing?
B) VOQ maintains separate queues for each output per input, eliminating HOL blocking.
Q11. Which of the following is a characteristic of the shared memory switch fabric?
B) Shared memory switches use a central scheduler to manage memory access; only one packet is processed at a time.
Q12. In an output‑queued switch, where does packet loss occur?
C) Packets are dropped when the output queue is full.
Q13. Which of the following is NOT a typical output scheduling algorithm?
C) RED is a drop policy, not a scheduling algorithm.
Q14. What is the role of the TTL (Time‑To‑Live) field in the IP header during forwarding?
B) TTL is decremented at each hop; when it reaches zero, the packet is discarded to prevent routing loops.
Q15. Which switching fabric type typically has the highest cost per port?
C) Crossbar switches have higher cost due to complex hardware and scheduling.
Q16. Explain the difference between the RIB and the FIB in a router.
The Routing Information Base (RIB) stores all known routes, including multiple paths and metric information, as learned from routing protocols. The Forwarding Information Base (FIB) is a subset of the RIB optimized for fast lookup; it contains the best routes for forwarding and is used by the data plane. The FIB is distributed to input ports for per‑packet forwarding decisions.
Q17. Describe the concept of "speedup" in a switch fabric and why it is used.
Speedup means operating the internal switching fabric at a higher rate than the input/output line rate (e.g., 2× speedup). This reduces internal contention and allows the switch to handle bursts more effectively, enabling higher throughput and lower loss.
Q18. Why is TCAM preferred for forwarding table lookups over traditional hash tables?
TCAM allows parallel search of all entries in a single clock cycle, supporting longest‑prefix matching efficiently. Hash tables typically require multiple memory accesses and cannot handle longest‑prefix matching as directly. TCAM is deterministic and provides constant lookup time, which is critical for wire‑speed forwarding.
Q19. Explain the difference between store‑and‑forward and cut‑through switching in the context of router latency.
Store‑and‑forward switches receive the entire packet before forwarding, which adds latency but allows error checking. Cut‑through switches start forwarding as soon as the destination address is read, reducing latency but may forward corrupted packets. Cut‑through is used in some high‑performance routers to minimize latency.
Q20. What is bufferbloat and how does it relate to router buffering?
Bufferbloat is the phenomenon where excessively large buffers in network devices cause high latency and jitter, especially for interactive applications. This occurs because large buffers absorb bursts but also hold packets for long times. Bufferbloat can be mitigated by using active queue management (AQM) like RED or by configuring smaller buffers.
Q21. A router has a crossbar switch fabric with 8 input ports and 8 output ports. The crossbar can switch a packet every 100 ns. If the line rate is 10 Gbps and the average packet size is 1500 bytes, what is the maximum throughput if only one packet can be switched at a time? What if the crossbar can switch up to 4 packets simultaneously?
One packet at a time: 100 ns = 1e-7 s. Packets/sec = 1e7. Throughput = 1e7 * 1500*8 = 1.2e11 bps = 120 Gbps.
4 packets simultaneously: 4 * 120 Gbps = 480 Gbps. However, actual throughput limited by line rates and input/output contention.
Q22. Consider a router using input queuing with HOL blocking. Under heavy uniform traffic, what is the maximum achievable throughput?
The maximum throughput for an input‑queued switch with HOL blocking under uniform traffic is approximately 58.6% (2 - √2). This is due to output contention and the blocking effect.
Q23. An enterprise router uses a shared bus switching fabric. The bus operates at 40 Gbps. The router has 4 input ports and 4 output ports, each at 10 Gbps. What is the aggregate throughput capacity and is it sufficient to handle full line rate traffic from all ports simultaneously?
Total input capacity = 4 * 10 Gbps = 40 Gbps. The shared bus can handle 40 Gbps, so in theory it can support full line rate if all traffic is evenly distributed. However, the bus is a single resource, so output contention and scheduling may cause loss. The aggregate throughput is limited to 40 Gbps.
Q24. A router uses a two‑stage pipeline for forwarding: Stage 1 performs header validation and TTL decrement, Stage 2 performs forwarding lookup. If each stage takes 50 ns, what is the maximum packet processing rate? What is the latency for a single packet?
Each stage takes 50 ns; with two stages, the pipeline can process one packet every 50 ns (the stage time) because stages overlap. Thus, processing rate = 1 / (50e-9) = 20 million packets per second. Latency for a single packet = 2 * 50 ns = 100 ns (since it goes through both stages sequentially).
Q25. A router is experiencing high packet loss due to output queue overflow. Propose three possible solutions and discuss their trade‑offs.
1. Increase buffer size: Reduces loss but increases latency and cost.
2. Implement active queue management (RED): Smoothly signals congestion, but may drop packets early.
3. Increase output link speed: Reduces queue build‑up but requires hardware upgrades.
4. Use priority queueing: Protects important traffic but may starve low‑priority traffic.
Q26. In a router with virtual output queuing (VOQ), explain how HOL blocking is eliminated. What is the trade‑off compared to simple input queuing?
VOQ maintains per‑output queues at each input port, so a packet destined for a blocked output does not block packets destined for other outputs. The trade‑off is increased queue management complexity and memory, as well as the need for a more complex scheduling algorithm to coordinate between input and output queues.
Q27. Compare the performance of a shared memory switch versus a crossbar switch in terms of scalability to high port counts.
Shared memory switches are limited by memory bandwidth, which grows linearly with port count and line rate. They become impractical for large port counts. Crossbar switches scale better because they provide multiple parallel paths, though they require complex scheduling. Crossbars are used in high‑end routers with many ports.
Q28. Explain how the routing processor updates the FIB in the input ports without interrupting forwarding.
Most routers use a dual‑FIB approach: a primary FIB actively used for forwarding, and a secondary FIB that is updated. Once the update is complete, a pointer switch occurs atomically, so the new FIB becomes active without packet loss. This is called "hitless" FIB update.
Q29. In a programmable data plane using P4, how does the router handle new protocols that were not originally supported in hardware?
P4 allows the network operator to define custom header formats and processing logic. The P4 program is compiled into a target‑specific configuration (e.g., for a switch ASIC) that reconfigures the data plane pipeline. This enables support for new protocols without hardware replacement.
Q30. What is the difference between cut‑through and store‑and‑forward switching, and in which scenarios might each be preferred?
Cut‑through starts forwarding as soon as the destination address is read, reducing latency; it is preferred in low‑latency environments like high‑frequency trading. Store‑and‑forward receives the entire packet, allowing error checking; it is preferred in environments where data integrity is critical, such as in core routers.
Q31. A router has a line rate of 100 Gbps and uses a 1.5 µs packet processing time per packet. What is the maximum packet arrival rate if packet size is 64 bytes? Is this sufficient for line rate?
64 bytes = 512 bits. Line rate packets/sec = 100e9 / 512 ≈ 195.3 million packets per second. Processing time: 1.5 µs = 1.5e-6 s, so max processed packets/sec = 1 / 1.5e-6 ≈ 666,667 packets/sec. This is far below the line rate requirement, so the router cannot process at wire speed for small packets.
Q32. What is the purpose of the link‑layer processing at the input port, and why is it performed before forwarding?
Link‑layer processing extracts the network‑layer datagram from the frame, ensures the frame is valid (checksum), and strips off the link‑layer headers. This must be done before forwarding because the forwarding decision is based on the network‑layer header (IP address).
Q33. Why do high‑end routers use distributed forwarding instead of a centralized CPU‑based forwarding?
Distributed forwarding allows each input port to make forwarding decisions in parallel, achieving much higher aggregate throughput than a single CPU. It also reduces the load on the routing processor, which can focus on control plane functions.
Q34. In the context of output scheduling, what is the difference between strict priority queueing and weighted fair queueing in terms of fairness and performance?
Strict priority gives absolute priority to higher‑priority queues, which can starve lower‑priority traffic. WFQ provides a weighted allocation of bandwidth, ensuring that each queue gets a fair share (proportional to weight) even under congestion, providing more fairness.
Q35. A router uses a crossbar switch with a speedup of 2. What does this mean and how does it affect performance?
A speedup of 2 means the internal switching fabric operates at twice the line rate (e.g., 2× the port speed). This reduces contention and allows the switch to handle bursts more effectively, potentially achieving 100% throughput even with output contention, because the fabric can accept packets faster than they arrive.
A router has 4 input ports and 4 output ports, each at 1 Gbps. The switching fabric is a crossbar with a switching time of 200 ns per packet. If all inputs are sending packets to different outputs at full line rate, what is the aggregate throughput? If all inputs send to the same output, what is the throughput?
Different outputs: Crossbar can switch all 4 packets simultaneously (non‑blocking), aggregate throughput = 4 Gbps (line rate).
Same output: Only one packet can be forwarded to that output at a time (output contention). Aggregate throughput = 1 Gbps (limited by the output port).
Explain how Virtual Output Queuing (VOQ) eliminates HOL blocking. Draw a simple diagram showing the queuing structure at an input port with 3 output ports.
VOQ maintains separate queues for each output port at each input port. Thus, if the queue for output 1 is blocked, packets for output 2 and 3 are in separate queues and can be forwarded independently. Diagram: Input port with 3 VOQs (Q1, Q2, Q3) each feeding into the switch fabric scheduler that arbitrates among them.
A router uses an input‑queued switch with HOL blocking. Under uniform traffic, the throughput is about 58.6%. If the router has 4 ports and each port is 10 Gbps, what is the effective throughput of the router? What would the throughput be if VOQ were used?
Total line rate = 4 * 10 = 40 Gbps. With HOL blocking, effective throughput ≈ 0.586 * 40 = 23.44 Gbps. With VOQ, if the switch fabric is non‑blocking, the router can achieve close to 40 Gbps (assuming no output contention).
A router uses a shared bus with a bandwidth of 20 Gbps. There are 5 input ports, each at 5 Gbps. What is the maximum aggregate throughput? Is the bus a bottleneck?
Total input capacity = 5 * 5 = 25 Gbps. The bus is limited to 20 Gbps, so the maximum aggregate throughput is 20 Gbps, making the bus the bottleneck.
Describe the packet processing pipeline in a modern router from arrival to departure. Identify which functions are performed at each stage and whether they are part of the data plane or control plane.
Stages: (1) Physical layer (line termination) – data plane; (2) Link‑layer processing – data plane; (3) Forwarding lookup – data plane; (4) Switching – data plane; (5) Output queue – data plane; (6) Link‑layer encapsulation – data plane; (7) Transmission – data plane. The routing processor (control plane) updates the FIB asynchronously.
Calculate the buffer size needed for an output port that has a link speed of 10 Gbps and an average RTT of 50 ms, assuming the buffer should hold at least one RTT's worth of data.
Buffer size = bandwidth × RTT = 10e9 bps * 0.05 s = 5e8 bits = 62.5 MB.
Compare the performance of FIFO, Priority Queueing (PQ), and Weighted Round‑Robin (WRR) in terms of fairness and delay for different traffic classes.
FIFO: no differentiation; all flows share delay. PQ: higher priority flows get lower delay, but lower priority can starve. WRR: provides weighted fairness; each class gets a guaranteed share of bandwidth, leading to more predictable delay for all.
A router has a TCAM that can store 512K entries. The forwarding table has 400K routes. Explain how the router handles forwarding lookups with such a TCAM.
The TCAM can store all 400K routes with room to spare. The lookup is performed by feeding the destination address into the TCAM, which returns the matching entry (longest prefix) in a single cycle. The TCAM is programmed with prefix entries ordered by priority.
Explain why output port buffering does not suffer from HOL blocking, and why it may still cause packet loss.
Output buffering stores packets after they have been switched, so each output queue is independent; a blocked packet in one output queue does not affect others. However, if the output queue fills up, packets are dropped (tail drop).
A router uses a two‑stage pipeline: Stage A takes 40 ns, Stage B takes 60 ns. What is the maximum packet processing rate and the latency per packet?
Pipeline rate is limited by the slowest stage: 60 ns per packet. Rate = 1 / 60e-9 = 16.67 million packets/sec. Latency per packet = 40 + 60 = 100 ns (store‑and‑forward through both stages).
In a router with a shared memory switch, the memory bandwidth is 100 Gbps. There are 8 input ports and 8 output ports, each at 10 Gbps. Is the memory bandwidth sufficient to support full line rate? Assume packets are 1500 bytes and switching requires reading from memory and writing to memory (2 memory operations per packet).
Total line rate = 8 * 10 Gbps = 80 Gbps. Each packet requires a memory read (input) and a memory write (output), so effective bandwidth needed is 2 * 80 = 160 Gbps. The memory bandwidth is only 100 Gbps, so it is insufficient; the switch is bottlenecked.
What is the purpose of the IP header checksum, and why is it recalculated at each hop?
The checksum ensures integrity of the IP header. It is recalculated at each hop because the TTL field changes (decremented), so the checksum must be updated to reflect the new header.
A router uses an active queue management scheme like RED. Explain how RED helps in avoiding global synchronization of TCP flows.
RED drops packets probabilistically before the queue is full, based on average queue length. This causes some TCP flows to reduce their sending rates gradually, avoiding the simultaneous backoff that occurs with tail drop (global synchronization). RED promotes a more even distribution of losses across flows.
Design a simple scheduling policy that gives priority to VoIP traffic while ensuring that best‑effort data traffic gets at least 30% of the bandwidth. Justify your design.
Use a combination of priority queueing for VoIP (high priority) and Weighted Round‑Robin (WRR) for data traffic. The WRR weights can be set to allocate, for example, 30% of bandwidth to data. To prevent VoIP from starving data, a rate limiter can be placed on VoIP, or a maximum bandwidth can be assigned to the priority queue.
Explain the concept of "in‑network computing" in the context of programmable data planes. Give an example of a function that could be offloaded to the data plane.
In‑network computing refers to performing application‑level processing on packets as they traverse the network, rather than at end hosts. For example, a switch could compute aggregate statistics (like average of sensor readings) and forward only the result, reducing bandwidth. This is enabled by programmable data planes (P4) that can execute custom logic on packets.
Research the architecture of the Cisco 8000 series or Juniper MX series routers. Write a 500‑word report comparing their switching fabric and forwarding architecture. Include details on line cards, fabric capacity, and forwarding performance.
Cisco 8000: Uses a distributed architecture with line cards and a programmable ASIC (Silicon One). The fabric is a high‑speed Clos network (hierarchical crossbar). Supports up to 100 Gbps and 400 Gbps ports. Forwarding uses TCAM and P4‑programmable pipeline.
Juniper MX: Uses a modular chassis with line cards and a central switch fabric (e.g., Juniper Trio chipset). Supports up to 100 Gbps ports. Uses a combination of TCAM and algorithmic lookup. Both routers emphasize high throughput, low latency, and programmability.
Explain the difference between input queuing and output queuing in terms of memory requirements and performance. Under what traffic conditions is output queuing preferred?
Input queuing requires buffers at each input port, which can be smaller because only one input's traffic may be buffered. However, it suffers from HOL blocking. Output queuing requires buffers at each output port, which may need to hold traffic from all inputs simultaneously, requiring larger total memory. Output queuing provides better performance (no HOL blocking) and is preferred when high throughput and low loss are required, especially for delay‑sensitive traffic.
Calculate the maximum throughput of a crossbar switch with N ports, line rate R, and a switching speed of S packets per second, assuming packet size is fixed at L bits. Discuss the impact of output contention.
Maximum throughput = N * R (if no contention). With output contention, the effective throughput is limited by the fact that multiple inputs cannot send to the same output simultaneously. In the worst case (all to one output), throughput = R. The scheduling algorithm determines how contention is resolved.
Describe the role of the routing processor in updating the FIB. What mechanisms are used to ensure that forwarding continues without interruption during updates?
The routing processor runs routing protocols, builds the RIB, and then selects the best routes to install in the FIB. To avoid disruption, routers often use a dual‑FIB scheme: a primary FIB for forwarding and a secondary FIB being updated. Once the update is complete, a pointer switch makes the new FIB active atomically. This is known as "hitless" or "in‑service" software upgrade (ISSU) for FIB updates.
Compare and contrast the following scheduling algorithms: FIFO, Priority Queueing, Weighted Round‑Robin, and Weighted Fair Queueing. For each, give a scenario where it would be the most appropriate choice.
FIFO: simple, appropriate for networks with undifferentiated traffic. Priority: appropriate when critical traffic (e.g., VoIP) must be served before others, but may starve low priority. WRR: useful for providing weighted bandwidth shares to different traffic classes without strict priority. WFQ: provides fair allocation and is ideal when multiple flows need guaranteed service, as in integrated services networks.
Explain the concept of "line‑rate forwarding" and the technologies that enable it. What are the challenges in achieving line‑rate forwarding for small packets?
Line‑rate forwarding means the router can forward packets at the maximum speed of the input links without dropping. Technologies: TCAM for fast lookup, high‑speed switching fabrics (crossbar), pipelined ASICs, and distributed processing. For small packets (e.g., 64 bytes), the packet arrival rate is very high (e.g., 14.88 Mpps for 1 Gbps), which stresses lookup and switching speed; achieving this requires extremely fast hardware.
Describe how a router handles a packet when the TTL field reaches zero. What ICMP message is sent, and what happens to the packet?
When TTL reaches zero, the router discards the packet and sends an ICMP Time Exceeded message (type 11, code 0) back to the source address. This prevents packets from looping endlessly and is used by traceroute.
Explain the role of the IP checksum in the forwarding path. Why is it not necessary to check the payload?
The IP header checksum ensures the integrity of the header only, not the payload. The payload is the responsibility of the transport layer (e.g., TCP checksum). Recalculating the checksum at each hop is efficient because only the header changes (TTL). Checking the payload would be too costly and is unnecessary because end‑to‑end error detection is provided by transport protocols.
Analyze the trade‑offs between using a shared memory switch fabric and a crossbar switch fabric for a router that needs to support 100 Gbps per port with 32 ports.
Shared memory would require memory bandwidth of at least 2 * 32 * 100 Gbps = 6.4 Tbps (read and write), which is extremely challenging and expensive. Crossbar switches scale better as they provide parallel paths, but they require complex scheduling. For 32 ports, a crossbar with internal speedup would be the preferred choice, although cost is higher.
Describe the concept of "packet classification" and how it relates to forwarding and scheduling. Give an example of a classification rule.
Packet classification is the process of categorizing packets based on header fields (e.g., source IP, destination IP, port numbers) to apply different forwarding or scheduling policies. It is used in firewalls, QoS, and routing policy. Example rule: "If destination port = 80, forward to queue 2 with high priority."
Explain the difference between centralized and distributed forwarding architectures. Give an example of a router that uses each.
Centralized forwarding uses a single processor (usually the routing processor) to handle all forwarding decisions; used in low‑end routers. Distributed forwarding uses multiple processing engines (often on line cards) to make forwarding decisions in parallel; used in high‑end routers like Cisco CRS or Juniper T series.
What is the purpose of the "don't care" (X) state in TCAM? How does it enable longest‑prefix matching?
In TCAM, each bit can be 0, 1, or X (don't care). For a routing table entry with prefix length /24, the first 24 bits are specified, and the remaining bits are X. When a destination address is presented, the TCAM compares and returns the first matching entry (ordered by prefix length). This allows longest‑prefix matching because entries with longer prefixes have fewer X's and are more specific.
Describe the concept of "cut‑through switching" and explain its advantages and disadvantages compared to store‑and‑forward switching in a router.
Cut‑through switching starts forwarding a packet as soon as the destination address is read, without waiting for the entire packet. This reduces latency. Disadvantages: may forward corrupted packets (since no error checking), and may cause issues if the input and output speeds differ. Store‑and‑forward checks the entire packet for errors before forwarding, increasing latency but ensuring integrity.
Research the concept of "bufferbloat" and propose two mitigation techniques that can be implemented in the data plane of a router.
Bufferbloat is high latency caused by oversized buffers. Mitigation: 1) Use Active Queue Management (RED, CoDel) to drop packets before the buffer is full, keeping queues short. 2) Configure smaller buffer sizes or use per‑flow fair queuing to prevent a single flow from filling the buffer.
Explain the role of the forwarding engine (FE) in a distributed router architecture. How does the FE interact with the routing processor?
The forwarding engine is the hardware component on each line card that performs per‑packet forwarding (lookup, switching). The routing processor computes the FIB and downloads it to the FEs. The FEs operate independently for forwarding, but they send exception packets (e.g., TTL expired) to the routing processor for software handling. The interaction is via a control channel (e.g., PCIe, Ethernet) that carries FIB updates and control messages.
This expanded tutorial has provided an in‑depth examination of router architecture and packet forwarding. Key takeaways include:
Understanding these concepts is crucial for later topics such as forwarding algorithms, IP addressing, fragmentation, and SDN.